1. Field of the Invention
The present invention generally relates to a clock recovery and frequency synthesizer timing loop and more particularly to an improved circuit for controlling loop dynamics of phase locked loops used in clock recovery and frequency synthesis.
2. Description of the Related Art
Conventional systems utilize phase locked loops (PLLs) for a wide range of purposes. For example, frequency synthesizers and clock recovery circuits are used in computer storage systems (such as optical, magnetic, and the like). A phase-locked-loop frequency synthesizer normally generates the frequency at which the data is written for hard disk drives. The same frequency is recovered from the data by a clock recovery PLL in the hard disk drive. The PLL includes a phase detector for generating a phase error estimate based on the difference between the estimated samples and the read signal samples. A PLL loop controller filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate. Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
Phase-locked loops in hard disk drive read channel integrated circuits (ICs) are generally required to operate over a two-to-one frequency range, while maintaining low clocking jitter characteristics. The synthesizer circuit often uses a voltage controlled oscillator (VCO) or current controlled oscillator (ICO) to produce the desired clocking frequency, such that the oscillator frequency, fosc, is a rational multiple, N/D of the externally generated reference frequency, fref. The PLL loop gain of a sampled data system may change with operating frequency. In signal processing terminology, the coefficients in the z or discrete frequency domain may depend on the sampling period, T, in the description of the loop dynamics. For this reason, the loop response may change with respect to the sampling period. It is desirable to maintain constant loop corrections/gain over the desired operating frequency range to maintain constant synthesizer loop dynamics. For example, if the loop has a lock-in time of 12 bytes at a 200 MHz data rate the lock-in time should be 12 bytes at 400 Mhz. Note that in the case of the higher data rate, the lock-in time is halved but is the same when measured in bit intervals. The purpose of the compensation this invention provides is to maintain constant loop response when measured in bit intervals.
However, conventional frequency synthesizers are formed using bipolar transistors. A bipolar arrangement is illustrated in FIG. 1 and is discussed below. Fabrication of devices using complementary metal oxide semiconductor (CMOS) technology is becoming more popular because of the reduced cost, reduced size, and increased yield associated with CMOS devices. Therefore, there is a need for a viable oscillator structure which can be manufactured using CMOS technology. The invention described below addresses this need and provides a unique oscillator control in a CMOS structure.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional oscillator controller, the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved oscillator controller that keeps the dynamic behavior of the timing loop constant on a per bit basis over all operating frequencies.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention a complementary metal oxide semiconductor PLL that includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.
The proportional signal and the integral signal are summed and multiplied by the same scaling factor of the calibration amplifier and the bandwidth amplifier. The proportional signal and the integral signal are scaled with changes in the reference frequency. The integral path includes multiple amplifiers, such that the proportional signal is scaled by the reference frequency and the integral signal is scaled by the reference frequency squared. The feedback loop has a dynamic behavior that is constant on a per bit basis over all operating frequencies. The calibration amplifier and the bandwidth amplifier scale the proportional signal and the integral signals as a percent of oscillator bias current.